1. Field of the Invention
This invention relates generally to microelectronics fabrications and, in particular, to methods of forming conducting interconnect structures that are protected from diffusion of chemical species into and out of surrounding materials.
2. Description of the Related Art
As the structures comprising integrated microelectronic circuitry continue to decrease in size, the conducting interconnects between them decrease in size as well. Smaller conducting interconnects must be composed of materials with higher conductivity and greater mechanical integrity, which presently favors the use of copper (Cu), with twice the conductivity of aluminum and three times the conductivity of tungsten, as the material of choice. Unfortunately, copper has been found to contaminate many of the materials used in integrated circuit fabrications, so special care must be taken to keep it from migrating into surrounding regions.
Several methods have been developed to provide containment of copper deposited as conducting leads and interconnects. Chief among these is the prior formation of diffusion barriers and liner layers within the trenches and vias into which the copper is subsequently deposited. Copper inlays surrounded by layers of other metals and their compounds such as tungsten, tantalum, molybdenum and titanium nitride, are called copper damascene structures.
Although the damascene process is an important step forward in forming viable copper interconnects, it does have problems associated with it which must be addressed. The barrier layer may itself be subject to degradation from surrounding materials. The barrier layer may not adhere well to the copper or to the surrounding material. The barrier layer may adversely affect the contact between the interconnect and other conducting layers. The barrier layer may be difficult to fabricate with the requisite thinness in small trenches and vias. With regard to the affect of surrounding materials on the barrier layer, it should be pointed out that fluorinated materials such as amorphous fluorinated carbon, PTFE, fluorinated polyimide and fluorinated silicon dioxide are presently being used as interlayer dielectrics because their low dielectric constants (low-k) tend to reduce parasitic capacitance between neighboring conducting lines and vias. When fluorinated materials are subjected to high temperature processing (above 300.degree. C.), which is quite common in the complex fabrication schemes of integrated microelectronic circuitry, the fluorine tends to out-diffuse into previously deposited metallic barrier layers and form metallic fluoride compounds (eg., fluorine diffusing into tantalum forms tantalum fluoride, TaF). These compounds degrade the adhesion and integrity of the metallic layers and lead to their delamination.
Several of the aforementioned problems have been addressed by recent inventions. Nguyen et al (U.S. Pat. No. 5,904,565) teach a damascene process which allows a direct copper to copper connection between vias on different but contiguous levels of an integrated circuit. Their method involves removal of the bottom portion of the barrier layer with an anisotropic etch, so that the copper inlay is put into direct contact with the upper portion of the copper inlay on the level below it. Teong (U.S. Pat. No. 5,693,563) teaches an alternative method for solving the same double level contact problem, wherein two barrier layers are used to enhance the connection properties. Iguchi et al (U.S. Pat. No. 5,744,394) teach a method for interconnecting a series of transistors in an integrated circuit fabrication wherein the interconnection layer is connected to the transistors through a barer layer which can be formed of any one of a number of metals or their compounds. Stolmeijer (U.S. Pat. No. 5,834,845) teaches a method for fabricating a multilevel interconnect structure composed of similar patterned metal layers as building blocks. These blocks are then connected by tungsten or aluminum plugs surrounded by titanium (Ti) or titanium nitride (TiN) barrier layers. Jain et al (U.S. Pat. No. 5,741,626) teach a method of improving the fabrication process of dual damascene structures by coating the devices with an anti-reflective material. This coating then enhances the photolithography process and also acts a a barrier layer for the copper interconnects.
Although each of the above cited inventions teach applications and improvements of the damascene process, they fail to address certain specific difficulties associated with the intrinsic nature of the process. In its various embodiments, the present invention differs from those cited above by addressing the following issues: the degradation of metallic barrier layers by the out-diffusion of fluorine from fluorinated dielectrics into those layers, the difficulty of using metallic barrier layers to conformally line trenches and vias of dimension less than 0.15 microns and the use of a novel class of non-conducting barrier layers to improve the adhesion of metallic barrier layers and copper inlays to trench and via sidewalls when the dimensions of these formations are less than 0.15 microns.